Implementation of multimillion gate ASIC designs in cutting edge process technologies (28nm, 45nm, 65nm, 90nm)
Ownership of all aspects of physical design including floorplanning, place and route, clock distribution, parasitic extraction, timing closure, power and signal integrity analysis, DFM, and DRC/LVS sign-off.
Meeting highly challenging schedule, performance, and quality constraints.
Location : Bengaluru/Bangalore
Experience : 0 - 5 Years
Education : UG - Any Graduate - Any Specialization / PG - M.Tech
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Desired Profile:
Graduates with M.E (Microelectronics) degree from reputed institutes with 0 – 6 years experience
Required Skills / Experience:
Experience in ASIC tapeouts, preferably in 28nm, 45nm & 65nm, to leading foundries
Experience in Block / Chip level P & R.
Clear understanding and command over all aspects of physical design including technology, libraries, floorplan, timing, signal integrity and power dissipation.
Skill and efficiency in scripting using Tcl or perl desirable
Demonstrated ability to work in a team environment
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Engineer, Senior Physical Design at MARVELL
